module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);

    parameter IDLE = 3'd0;
    parameter S0 = 3'd1;
    parameter S1 = 3'd2;
    parameter S2 = 3'd3;
    parameter S3 = 3'd4;
    
    reg	[2:0]	state;
    reg	[2:0]	next_state;
    
    always @(posedge clk)
        begin
            if(reset)
                begin
                    state <= IDLE;
                end
            else
                begin
                    state <= next_state;
                end
        end
    
    always @(*)
        begin
            case(state)
                IDLE:	next_state = data ? S0 : IDLE;
                S0:		next_state = data ? S1 : IDLE;
                S1:		next_state = data ? S1 : S2;
                S2:		next_state = data ? S3 : IDLE;
                S3:		next_state = S3;
            endcase
        end
    
    assign start_shifting = (state == S3);
    
endmodule
